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Arms race: SiFive, Hex Five build code safe houses for RISC-V chips – ANITH
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Arms race: SiFive, Hex Five build code safe houses for RISC-V chips

Arms race: SiFive, Hex Five build code safe houses for RISC-V chips

Those developing custom CPUs can now tap a TrustZone-ish trusted execution environment

If you’ve been looking at SiFive’s RISC-V-based chip technology and thinking, y’know what, it’s missing an Arm TrustZone-style element to run sensitive code, well, here’s some good news.…

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Anith Gopal
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